UM0306 Power control (PWR)
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3.4.2 Power control/status register (PWR_CSR)
Address Offset: 04h
Reset Value: 0000 0000 0000 0000 (0000h) (not reset by wake-up from STANDBY mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved
EWUP Reserved PVDO SBF WUF
rw rrr
Bits 31:9 Reserved, always read as 0.
Bit 8
EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does
not wake-up the device from STANDBY mode.
1: WKUP pin is used for wake-up from STANDBY mode and forced in input
pull down configuration (rising edge on WKUP pin wakes-up the system from
STANDBY mode).
Note: This bit is reset by a system Reset.
Bits 7:3 Reserved, always read as 0.
Bit 2
PVDO: PVD Output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the
PVDE bit.
0: V
DD
is higher than the PVD threshold selected with the PLS[2:0] bits.
1: V
DD
is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by STANDBY mode. For this reason, this bit is equal
to 0 after STANDBY or reset until the PVDE bit is set.
Bit 1
SBF: STANDBY Flag
This bit is set by hardware and cleared only by a POR/PDR (Power On
Reset/Power Down Reset) or by setting the CSBF bit in the Power control
register (PWR_CR)
0: Device has not been in STANDBY mode
1: Device has been in STANDBY mode
Bit 0
WUF: Wake-Up Flag
This bit is set by hardware and cleared only by a POR/PDR (Power On
Reset/Power Down Reset) or by setting the CWUF bit in the Power control
register (PWR_CR)
0: No wake-up event occurred
1: A wake-up event was received from the WKUP pin or from the RTC alarm
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