UM0306 General purpose and alternate function I/O (GPIO and AFIO)
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5.4.2 External interrupt configuration register 1 (AFIO_EXTICR1)
Address offset: 08h
Reset value: 0000h
5.4.3 External interrupt configuration register 2 (AFIO_EXTICR2)
Address offset: 0Ch
Reset value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved
Bits 15:0
EXTIx[3:0]: EXTI x configuration (x= 0 to 3)
These bits are written by software to select the source input for EXTIx external
interrupt. Refer to Section 6.2.5: External interrupt/event line mapping on
page 103
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:16 Reserved
Bits 15:0
EXTIx[3:0]: EXTI x configuration (x= 4 to 7)
These bits are written by software to select the source input for EXTIx external
interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin