ST STM32F10 Series User Manual

UM0306 Real-Time Clock (RTC)
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Figure 20. RTC Overflow waveform example with PR=0003
8.4 RTC register description
Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.
8.4.1 RTC control register High (RTC_CRH)
Address Offset: 00h
Reset value: 0000h
These bits are used to mask interrupt requests. Note that at reset all interrupts are disabled,
so it is possible to write to the RTC registers to ensure that no interrupt requests are pending
after initialization. It is not possible to write to the RTC_CRH register when the peripheral is
completing a previous write operation (flagged by RTOFF=0, see Section 8.3.4 on page
124).
The RTC functions are controlled by this control register. Some bits must be written using a
specific configuration procedure (see Configuration procedure:).
RTC_CNT FFFFFFFB
FFFFFFFC
RTC_PR
0002 0001 0000 0003 0002 0001 0000 0003
FFFFFFFD
RTC_Overflow
0002 0001 0000 0003
FFFFFFFE
0002 0001 0000 0003
FFFFFFFF
0002 0001 0000 0003
OWF
can be cleared by software
RTC_Second
RTCCLK
0000
0002 0001 0000 0003
(not powered
in STANDBY)
1 RTCCLK
1514131211109876543210
Reserved OWIE ALRIE SECIE
rw rw rw
Bits 15:3 Reserved, forced by hardware to 0.
Bit 2
OWIE: OverfloW Interrupt Enable
0: Overflow interrupt is masked.
1: Overflow interrupt is enabled.
Bit 1
ALRIE: Alarm Interrupt Enable
0: Alarm interrupt is masked.
1: Alarm interrupt is enabled.
Bit 0
SECIE: Second Interrupt Enable
0: Second interrupt is masked.
1: Second interrupt is enabled.
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ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English