Advanced control timer (TIM1) UM0306
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12.5.18 Break and dead-time register (TIM1_BDTR)
Address offset: 44h
Reset value: 0000h
1514131211109876543210
MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15
MOE: Main Output enable.
This bit is cleared asynchronously by hardware as soon as the break input is active.
It is set by software or automatically depending on the AOE bit. It is acting only on
the channels which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE,
CCxNE in TIM1_CCER register).
See OC/OCN enable description for more details (Section 12.5.9: Capture/compare
enable register (TIM1_CCER) on page 209).
Bit 14
AOE: Automatic Output enable.
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break
input is not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed
(LOCK bits in TIM1_BDTR register).
Bit 13
BKP: Break Polarity.
0: Break input BRK is active low
1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed
(LOCK bits in TIM1_BDTR register).
Bit 12
BKE: Break enable.
0: Break inputs (BRK and BRK_ACTH) disabled
1; Break inputs (BRK and BRK_ACTH) enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed
(LOCK bits in TIM1_BDTR register).
Bit 11
OSSR: Off-State Selection for Run mode.
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is
implemented in the timer.
See OC/OCN enable description for more details (Section 12.5.9: Capture/compare
enable register (TIM1_CCER) on page 209).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as
CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed
(LOCK bits in TIM1_BDTR register).
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