UM0306 Independent watchdog (IWDG)
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10.2.2 Prescaler register (IWDG_PR)
Address Offset: 04h
Reset value: 00000000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved PR[2:0]
rw rw rw
Bits 31:3 Reserved, read as 0.
Bits 2:0
PR[2:0]: Prescaler divider
These bits are write access protected seeSection 10.1.2. They are written by
software to select the prescaler divider feeding the counter clock. PVU bit of
IWDG_SR must be reset in order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the VDD voltage
domain. This value may not be up to date/valid if a write operation to this register
is ongoing. For this reason the value read from this register is valid only when
the PVU bit in the IWDG_SR register is reset.
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