Reset and clock control (RCC) UM0306
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4.3.5 APB1 Peripheral reset register (RCC_APB1RSTR)
Address offset: 10h
Reset value: 0000 0000h
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
PWR
RST
BKP
RST
Res.
CAN
RST
Res.
USB
RST
I2C2
RST
I2C1
RST
Reserved
USART
3
RST
USART
2
RST
Res.
rw rw rw rw rw rw rw rw
1514131211109 8765432 1 0
Res.
SPI2
RST
Reserved
WWD
GRST
Reserved
TIM4
RST
TIM3
RST
TIM2
RST
rw rw rw rw rw
Bits 31:29 Reserved, always read as 0.
Bit 28
PWRRST Power interface reset
Set and reset by software.
0: No effect
1: Reset power interface
Bit 27
BKPRST Backup interface reset
Set and reset by software.
0: No effect
1: Reset backup interface
Bit 26 Reserved, always read as 0.
Bit 25
CANRST CAN reset
Set and reset by software.
0: No effect
1: Reset CAN
Bit 24 Reserved, always read as 0.
Bit 23
USBRST USB reset
Set and reset by software.
0: No effect
1: Reset USB
Bit 22
I2C2RST I2C 2 reset
Set and reset by software.
0: No effect
1: Reset I2C 2
Bit 21
I2C1RST I2C 1 reset
Set and reset by software.
0: No effect
1: Reset I2C 1