DMA controller (DMA) UM0306
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7.3.2 Arbiter
The arbiter manages the channel requests based on their priority and launches the
peripheral/memory access sequences.
The priorities are managed in two stages:
● Software: each channel priority can be configured in the DMA_CCRx register. There
are four levels:
– Very high priority
– High priority
– Medium priority
–Low priority
● Hardware: if 2 requests have the same software priority level, the channel with the
lowest number will get priority versus the channel with the highest number. For
example, channel 2 gets priority over channel 4.
7.3.3 DMA channels
Each channel can handle DMA transfer between a peripheral register located at a fixed
address and a memory address. The amount of data to be transferred (up to 65535) is
programmable. The register which contains the amount of data items to be transferred is
decremented after each transaction.
Programmable data sizes
Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE
and MSIZE bits in the DMA_CCRx register.
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after
each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If
incremented mode is enabled, the address of the next transfer will be the address of the
previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer
address will be the one programmed in the DMA_CPARx/DMA_CMARx registers.
If the channel is configured in non-circular mode, no DMA requests are served after the end
of the transfer (i.e. once the number of data to be transferred reaches zero).
Channel configuration procedure
The following sequence should be followed to configure a DMA channel (where x is the
channel number).
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