UM0306 Independent watchdog (IWDG)
139/519
Figure 21. Independent watchdog block diagram
Note: The watchdog function is implemented in the VDD voltage domain that is still functional in
STOP and STANDBY modes.
Note: These timings are given for a 32 kHz clock but the microcontroller’s internal RC frequency
can vary from 30 to 90 kHz. Moreover, given an exact RC oscillator frequency, the exact
timings still depend on the phasing of the APB interface clock versus the RC oscillator 32
kHz clock so that there is always a full RC period of uncertainty.
10.2 IWDG register description
Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.
10.2.1 Key register (IWDG_KR)
Address Offset: 00h
Reset value: 00000000h (reset by STANDBY mode)
IWDG RESET
Prescaler
12-bit Down-counter
IWDG_PR
Prescaler Register
IWDG_RLR
Reload Register
8-bit
LSI
IWDG_KR
Key Register
1.8 V voltage domain
VDD voltage domain
IWDG_SR
Status Register
12-bit reload value
(32 kHz)
Table 33. Watchdog time-out period (with 32 kHz input clock)
Prescaler Divider PR[2:0] bits
Min Time-out
RL[11:0]= 000h
Max Time-out
RL[11:0]= FFFh
/4 0 0.125 ms 512.5 ms
/8 1 0.25 ms 1025 ms
/16 2 0.50 ms 2050 ms
/32 3 1 ms 4100 ms
/64 4 2 ms 8200 ms
/128 5 4 ms 16400 ms
/256 6 (or 7) 8 ms 32800 ms
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
KEY[15:0]
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