Independent watchdog (IWDG) UM0306
138/519
10 Independent watchdog (IWDG)
The STM32F10x has two embedded watchdog peripherals which offer a combination of
high safety level, timing accuracy and flexibility of use. Both Watchdog peripherals
(Independent and Window) serve to detect and resolve malfunctions due to software failure,
and triggering an interrupt or system reset when the counter reaches a given time-out value.
The Independent Watchdog (IWDG) is clocked by its own dedicated low-speed clock (32
kHz) and thus stays active even if the main clock fails. The Window Watchdog (WWDG)
clock is prescaled from the APB1 clock and has a configurable time-window that can be
programmed to detect abnormally late or early application behavior.
The IWDG is best suited to applications which require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. The WWDG is best suited to applications which require the watchdog to react
within an accurate timing window.
For further information on the Window Watchdog, refer to Section 11 on page 145.
10.1 Introduction
Figure 21 shows the functional blocks of the independent Watchdog module.
When the independent watchdog is started by writing the value CCCCh in the Key Register
(IWDG_KR), the counter starts counting down from the reset value of FFFh. When it
reaches the end of count value (000h) a reset signal is generated (IWDG RESET).
Whenever the key value AAAAh is written in the IWDG_KR register, the IWDG_RLR value is
re-loaded in the counter and the watchdog reset is prevented.
10.1.1 Hardware watchdog
If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power on, and will generate a reset unless the Key register is
written by the software before the counter reaches end of count.
10.1.2 Register access protection
Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you
must first write the code 5555h in the IWDG_KR register. A write access to this register with
a different value will break the sequence and register access will be protected again. This
implies that it is the case of the reload operation (writing AAAAh)
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
10.1.3 Debug mode
When the microcontroller enters debug mode (Cortex-M3 core halted), the IWDG counter
either continues to work normally or stops, depending on DBG_IWDG_STOP configuration
bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and
watchdog and bxCAN.
To Next Page
Loading...
Need help?
General
