UM0306 Reset and clock control (RCC)
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4.3.9 Backup domain control register (RCC_BDCR)
Address: 20h
Reset value: 0000 0000h, reset by Backup domain Reset.
Access: 0 <= wait state <= 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register
(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write
protected and the DBP bit in the Power control register (PWR_CR)has to be set before
these can be modified. Refer to Section 9.1 on page 133 for further information. These bits
are only reset after a Backup domain Reset and V
BAT
power on. Any internal or external
Reset will not have any effect on these bits.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved BDRST
rw
1514131211109 87654321 0
RTC
EN
Reserved RTCSEL[1:0] Reserved
LSE
BYP
LSE
RDY
LSEON
rw rw rw rw r rw
Bits 31:17 Reserved, always read as 0.
Bit 16
BDRST Backup domain software reset
Set and reset by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15
RTCEN RTC clock enable
Set and reset by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, always read as 0.
Bits 9:8
RTCSEL[1:0] RTC clock source selection
Set by software to select the clock source for the RTC. These bits can be written
only once time. The BDRST bit can be used to reset them.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock
Bits 7:3 Reserved, always read as 0.
Bit 2
LSEBYP External Low Speed oscillator Bypass
Set and reset by software to bypass oscillator in debug mode. This bit can be
written only when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
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