Advanced control timer (TIM1) UM0306
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12.5.6 Event generation register (TIM1_EGR)
Address offset: 14h
Reset value: 0000h
1514131211109876543210
Reserved BG TG COM CC4G CC3G CC2G CC1G UG
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Bits 15:8 Reserved, always read as 0.
Bit 7
BG: Break Generation.
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related
interrupt or DMA transfer can occur if enabled.
Bit 6
TG: Trigger Generation.
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: The TIF flag is set in TIM1_SR register. Related interrupt or DMA transfer can
occur if enabled.
Bit 5
COM: Capture/Compare Control Update Generation.
This bit can be set by software, it is automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels having a complementary output.
Bit 4
CC4G: Capture/Compare 4 Generation.
refer to CC1G description
Bit 3
CC3G: Capture/Compare 3 Generation.
refer to CC1G description
Bit 2
CC2G: Capture/Compare 2 Generation.
refer to CC1G description
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