Reset and clock control (RCC) UM0306
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The timer clock frequencies are twice the frequency of the APB domain which they are
connected to. Nevertheless, if the APB prescaler is 1, the clock frequency of the timer is the
same as the frequency of the APB domain which it is connected to.
FCLK acts as Cortex-M3 free running clock. For more details refer to the ARM Cortex-M3
Technical Reference Manual.
4.2.1 HSE clock
The High Speed External clock signal (HSE) can be generated from two possible clock
sources:
● HSE external crystal/ceramic resonator
● HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 25
MHz. You select this mode by setting the HSEBYP and HSEON
bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 8.
Figure 8. HSE/ LSE clock sources
Hardware Configuration
External ClockCrystal/Ceramic Resonators
OSC_OUT
EXTERNAL
SOURCE
(HiZ)
OSC_IN OSC_OUT
LOAD
CAPACITORS
C
L2
C
L1
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