Window watchdog (WWDG) UM0306
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value is lower than the window register value. The value to be stored in the WWDG_CR
register must be between FFh and C0h:
● Enabling the watchdog:
he watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in
the WWDG_CR register, then it cannot be disabled again except by a reset.
● Controlling the downcounter:
This downcounter is free-running: It counts down even if the watchdog is disabled.
When the watchdog is enabled, the T6 bit must be set to prevent generating an
immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset. The timing varies between a minimum and a
maximum value due to the unknown status of the prescaler when writing to the
WWDG_CR register (see Figure 23).
The Configuration register (WWDG_CFR) contains the high limit of the window: To
prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 3Fh. Figure 23 describes the window watchdog
process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
11.4 How to program the watchdog timeout
Figure 23 shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 23.
Warning: When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
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