Serial peripheral interface (SPI) UM0306
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16.3 Functional description
16.3.1 General description
The block diagram of the SPI is shown in Figure 140.
Figure 140. SPI block diagram
Usually, the SPI is connected to external devices through 4 pins:
● MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode
and receive data in master mode.
● MOSI: Master Out / Slave In data. This pin can be used to transmit data in master
mode and receive data in slave mode.
● SCK: Serial Clock out by SPI masters and input by SPI slaves.
● NSS: Slave select. This is a optional pin to select master/ slave mode. This pin acts as
a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid
contention on the data lines. Slave NSS inputs can be driven by standard I/O ports on
the master Device. The NSS pin may also be used as an output if enabled (SSOE bit)
and driven low if the SPI is in master configuration. In this manner, all NSS pins from
devices connected to the Master NSS pin see a low level become slaves when they are
configured in NSS hardware mode.
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 141.
RX BUFFER
TX BUFFER
SHIFT REGISTER
LsbFirst
READ
WRITE
ADDRESS AND DATA BUS
MOSI
MISO
BAUD RATE GENERATOR
SCK
MASTER CONTROL LOGIC
COMMUNICATION
CONTROL
SPE BR2
BR1 BR0 MSTRCPOL CPHA
BR[2:0]
RXNE
LSB
BIDI
MODE
BIDI
OE
RX
SSM SSI
BSY OVR
MOD
RXNETXE
ERR
TXE
0
0
CRC
DFF
0SSOE
CRC
EN
0
ONLY
Next
CRC
ERR
0
1
NSS
IE
F
FIRST
SPI_CR1
SPI_CR2
SPI_SR
TXDM
AEN
RXDM
AEN
IEIE
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