UM0306 Serial peripheral interface (SPI)
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16 Serial peripheral interface (SPI)
16.1 Introduction
The Serial Peripheral Interface (SPI) allows half/ full-duplex, synchronous, serial
communication with external devices. The interface can be configured as the master and in
this case it provides the communication clock (SCK) to the external slave device. The
interface is also capable of operating in multi-master configuration.
It may be used for a variety of purposes, including Simplex synchronous transfers on 2 lines
with a possible bidirectional data line or reliable communication using CRC checking.
16.2 Main features
● Full duplex synchronous transfers on 3 lines
● Simplex synchronous transfers on 2 lines with or without a bidirectional data line
● 8- or 16-bit transfer frame format selection
● Master or slave operation
● Multi-master mode capability
● 8 Master mode baud rate prescalers (f
PCLK
/2 max.)
● Slave mode frequency (f
CPU
/2 max.)
● Faster communication for both master and slave: Max. SPI speed up to 18 MHz
● NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
● Programmable clock polarity and phase
● Programmable data order with MSB-first or LSB-first shifting
● Dedicated transmission and reception flags with interrupt capability
● SPI bus busy status flag
● Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– Automatic CRC error checking for last received byte in full duplex mode
● Master mode fault, overrun and CRC error flags with interrupt capability
● 1-byte transmission and reception buffer with DMA capability: Tx and Rx requests
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