General purpose timer (TIMx) UM0306
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Figure 74. Counter timing diagram with prescaler division change from 1 to 4
13.4.2 Counter modes
Up-counting mode
In up-counting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generate at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register
is set, setting the UG bit generates an update event UEV but without setting the UIF flag
(thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
CK_PSC
00
CNT_EN
TIMER CLOCK = CK_CNT
COUNTER REGISTER
UPDATE EVENT (UEV)
0
F9 FA FB FCF7
PRESCALER CONTROL REGISTER
03
Write a new value in TIMx_PSC
PRESCALER BUFFER
03
PRESCALER COUNTER
0
1 2 3 0 1 2 3
F8 01
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