Power control (PWR) UM0306
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3.3.4 STOP mode
The STOP mode is based on the Cortex-M3 deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode. In
STOP mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.
Entering STOP mode
Refer to Ta bl e 7 for details on how to enter STOP mode.
To further reduce power consumption in STOP mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the Power control register
(PWR_CR).
If Flash memory programming is ongoing, the STOP entry is delayed until the memory
access is finished.
If an access to APB domain is ongoing, STOP mode entry is delayed until the APB access is
finished.
In STOP mode, the following features can be selected by programming individual control
bits:
● Independent Watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 10.1 in Section 10: Independent watchdog (IWDG).
● Real-Time Clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR).
Exiting STOP mode
Refer to Ta bl e 7 for more details on how to exit STOP mode.
When exiting STOP mode by issuing an interrupt or a wake-up event, the HSI RC oscillator
is selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from STOP mode. By keeping the internal regulator ON during
STOP mode, the consumption is higher although the startup time is reduced.
Table 6. SLEEP-ON-EXIT mode
Mode Entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex-M3 System Control register.
Mode Exit
If WFI was used for entry:
Interrupt or Reset of Cortex Control register bit 1.
If WFE was used for entry:
Wake-up event: Refer to Section 6.2.3: Wake-up event management
Wake-up latency None
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