Real-Time Clock (RTC) UM0306
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8.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL)
The Prescaler Load registers keep the period counting value of the RTC prescaler. They are
write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if
the RTOFF value is ‘1’.
RTC prescaler load register high (RTC_PRLH)
Address Offset: 08h
Write only (see Section 8.3.4 on page 124)
Reset value: 0000h
RTC prescaler load register low (RTC_PRLL)
Address Offset: 0Ch
Write only (see Section 8.3.4 on page 124)
Reset value: 8000h
Note: If the input clock frequency (f
RTCCLK
) is 32.768 kHz, write 7FFFh in this register to get a
signal period of 1 second.
1514131211109876 5 43210
Reserved PRL[19:16]
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Bits 15:4 Reserved, forced by hardware to 0.
Bits 3:0
PRL[19:16]: RTC Prescaler Reload Value High
These bits are used to define the counter clock frequency according to the following
formula:
f
TR_CLK
= f
RTCCLK
/(PRL[19:0]+1)
Caution: The zero value is not recommended. RTC interrupts and flags cannot be
asserted correctly.
1514131211109876 5 43210
PRL[15:0]
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Bits 15:0
PRL[15:0]: RTC Prescaler Reload Value Low
These bits are used to define the counter clock frequency according to the following
formula:
f
TR_CLK
= f
RTCCLK
/(PRL[19:0]+1)
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