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3.3.5 STANDBY mode
The STANDBY mode allows to achieve the lowest power consumption. It is based on the
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
switched off. SRAM and register contents are lost except for registers in the Backup domain
and STANDBY circuitry (see Figure 3).
Entering STANDBY mode
Refer to Ta bl e 8 for more details on how to enter STANDBY mode.
In STANDBY mode, the following features can be selected by programming individual
control bits:
● Independent Watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 10.1 in Section 10: Independent watchdog (IWDG).
● Real-Time Clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR)
Exiting STANDBY mode
The microcontroller exits STANDBY mode when an external Reset (NRST pin), IWDG
Reset, a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after
wake-up from STANDBY except for Power control/status register (PWR_CSR).
After waking up from STANDBY mode, program execution restarts in the same way as after
a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power
control/status register (PWR_CSR) indicates that the MCU was in STANDBY mode.
Table 7. STOP mode
Mode Entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex-M3 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR
Note: To enter STOP mode, all EXTI Line pending bits (in Pending register
(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the STOP mode
entry procedure is ignored and program execution continues.
Mode Exit
If WFI was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 27: Vector
table on page 98
If WFE was used for entry:
Any EXTI Line configured in event mode. Refer to Section 6.2.3: Wake-
up event management on page 102
Wake-up latency None
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