UM0306 Analog/digital converter (ADC)
461/519
One of these events can be generated by setting a bit in a register (SWSTART and
JSWSTART in ADC_CR2).
A regular group conversion can be interrupted by a injected trigger.
19.9 DMA request
Since converted regular channels value are stored in a unique data register, it is necessary
to use DMA for conversion of more than one regular channel. This avoids the loss of data
already stored in the ADC_DR register.
Only the end of conversion of a regular channel generates a DMA request, which allows the
transfer of its converted data from the ADC_DR register to the destination location selected
by the user.
Table 67. External trigger for regular channels
Source Type EXTSEL[2:0]
Timer 1 CC1 output
Internal signal from on-chip
timers
000
Timer 1 CC2 output 001
Timer 1 CC3 output 010
Timer 2 CC2 output 011
Timer 3 TRGO output 100
Timer 4 CC4 output 101
External Interrupt 11 External pin 110
SWSTART Software control bit 111
Table 68. External trigger for injected channels
Source Connection Type JEXTSEL[2:0]
Timer 1 TRGO output
Internal signal from on-chip
timers
000
Timer 1 CC4 output 001
Timer 2 TRGO output 010
Timer 2 CC1 output 011
Timer 3 CC4 output 100
Timer 4 TRGO output 101
External Interrupt 15 External pin 110
JSWSTART Software control bit 111
To Next Page
Loading...
Need help?
General
