General purpose timer (TIMx) UM0306
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In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The auto-reload active register is updated with the preload value (content of the TIMx_ARR
register). Note that if the update source is a counter overflow, the auto-reload is updated
before the counter is reloaded, so that the next period is the expected one (the counter is
loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 86. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
Figure 87. Counter timing diagram, internal clock divided by 2
CK_INT
02
CNT_EN
TIMER CLOCK = CK_CNT
COUNTER REGISTER
UPDATE INTERRUPT FLAG (UIF)
COUNTER UNDERFLOW
UPDATE EVENT (UEV)
03 04 05 06 05 04 0303 02 01 00 0104
COUNTER UNDERFLOW
Note: Here, center-aligned mode 1 is used
0002 0000 0001 0002 0003
CNT_EN
TIMER CLOCK = CK_CNT
COUNTER REGISTER
UPDATE INTERRUPT FLAG (UIF)
0003
0001
COUNTER UNDERFLOW
UPDATE EVENT (UEV)
CK_INT
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