ST STM32F10 Series User Manual

UM0306 Serial peripheral interface (SPI)
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Figure 143. Data clock timing diagram
Data frame format
Data can be shifted out either MSB-first or LSB-first depending on the value of the
LSBFIRST bit in the SPI_CR1 Register.
Each data frame is 8 or 16 bits long depending on the size of the data programmed using
the DFF bit in the SPI_CR1 register. The selected data frame format is applicable for
transmission and/or reception.
16.3.2 SPI slave mode
In slave configuration, the serial clock is received on the SCK pin from the master device.
The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer
rate.
CPOL = 1
CPOL = 0
MSBit
LSBit
MSBit
LSBit
MISO
(from master)
MOSI
(from slave)
NSS
(to slave)
CAPTURE STROBE
CPHA =1
CPOL = 1
CPOL = 0
MSBit
LSBit
MSBit
LSBit
MISO
(from master)
MOSI
NSS
(to slave)
CAPTURE STROBE
CPHA =0
Note: These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.
(from slave)
8 or 16 bits depending on Data Frame Format (see SPI_CR1)
8 or 16 bits depending on Data Frame Format (see SPI_CR1)
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ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English