Serial peripheral interface (SPI) UM0306
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Procedure
1. Set the DFF bit to define 8- or 16-bit data frame format
2. Select the CPOL and CPHA bits to define one of the four relationships between the
data transfer and the serial clock (see Figure 143). For correct data transfer, the CPOL
and CPHA bits must be configured the same way in the slave device and the master
device.
3. The frame format (MSB-first or LSB-first depending on the value of the LSBFIRST bit in
the SPI_CR1 register) must be same as the master device.
4. In Hardware mode (refer to Slave select (NSS) pin management on page 361), the
NSS pin must be connected to a low level signal during the complete byte transmit
sequence. In Software mode, set the SSM bit and clear the SSI bit in the SPI_CR1
register.
5. Clear the MSTR bit and set the SPE bit (both in the SPI_CR1 register) to assign the
pins to alternate functions.
In this configuration the MOSI pin is a data input and the MISO pin is a data output.
Transmit sequence
The data byte is parallel loaded into the Tx buffer during a write cycle.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin. The remaining bits (the 7 bits in 8-bit data frame
format, and the 15 bits in 16-bit data frame format) are loaded into the shift-register. The
TXE flag in the SPI_SR register is set on the transfer of data from the Tx Buffer to the shift
register and an interrupt will be generated if TXEIE bit in the SPI_CR2 register is set.
For the receiver, when data transfer is complete:
● The Data in shift register is transferred to Rx Buffer and the RXNE flag (SPI_SR
register) is set
● An Interrupt is generated if the RXEIE bit is set in the SPI_CR2 register.
After the last sampling clock edge the RXNE bit is set, a copy of the data byte received in
the shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI
peripheral returns this buffered value.
Clearing of the RXNE bit is performed by reading the SPI_DR register.
16.3.3 SPI master mode
In a master configuration, the serial clock is generated on the SCK pin.
Procedure
1. Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register).
2. Select the CPOL and CPHA bits to define one of the four relationships between the
data transfer and the serial clock (see Figure 143).
3. Set the DFF bit to define 8- or 16-bit data frame format
4. Configure the LSBFIRST bit in the SPI_CR1 register to define the frame format
5. If the NSS pin is required in input mode, in Hardware mode, connect the NSS pin to a
high level signal during the complete byte transmit sequence. In software mode, set the
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