General purpose timer (TIMx) UM0306
232/519
Figure 91. Counter timing diagram, Update event with ARPE=1 (counter overflow)
13.4.3 Clock selection
The counter clock can be provided by the following clock sources:
● Internal clock (CK_INT)
● External clock mode1: external input pin (TIx)
● External clock mode2: external trigger input (ETR)
● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to : Using
one timer as prescaler for the another on page 252 for more details.
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 92 shows the behavior of the control circuit and the up-counter in normal mode,
without prescaler.
36
CNT_EN
TIMER CLOCK = CK_CNT
COUNTER REGISTER
UPDATE INTERRUPT FLAG (UIF)
COUNTER OVERFLOW
UPDATE EVENT (UEV)
35 34 33 32 31 30 2FF8 F9 FA FB FCF7
AUTO-RELOAD PRELOAD REGISTER
FD 36
Write a new value in TIMx_ARR
AUTO-RELOAD ACTIVE REGISTER
FD 36
CK_INT
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