Advanced control timer (TIM1) UM0306
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12.5.19 DMA control register (TIM1_DCR)
Address offset: 48h
Reset value: 0000h
12.5.20 DMA address for burst mode (TIM1_DMAR)
Address offset: 4Ch
Reset value: 0000h
1514131211109876543210
Reserved DBL[4:0] Reserved DBA[4:0]
rw rw rw rw rw rw rw rw rw rw
Bits 15:13 Reserved, always read as 0
Bits 12:8
DBL[4:0]: DMA Burst Length.
This 5-bit vector defines the length of DMA transfers in burst mode (the timer
recognizes a burst transfer when a read or a write access is done to the TIM1_DMAR
address), i.e. the number of bytes to be transferred.
00000: 1 byte,
00001: 2 bytes,
00010: 3 bytes,
...
10001: 18 bytes.
Bits 7:5 Reserved, always read as 0
Bits 4:0
DBA[4:0]: DMA Base Address.
This 5-bits vector defines the base-address for DMA transfers in burst mode (when
read/write access are done through the TIM1_DMAR address). DBA is defined as an
offset starting from the address of the TIM1_CR1 register.
Example:
00000: TIM1_CR1,
00001: TIM1_CR2,
00010: TIM1_SMCR,
...
1514131211109876543210
DMAB[15:0]
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Bits 15:0
DMAB[15:0]: DMA register for burst accesses.
A read or write access to the DMAR register accesses the register located at the
address:
“(TIM1_CR1 address) + DBA + (DMA index)” in which:
TIM1_CR1 address is the address of the control register 1,
DBA is the DMA base address configured in TIM1_DCR register,
DMA index is the offset automatically controlled by the DMA transfer, depending on
the length of the transfer DBL in the TIM1_DCR register.
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