DMA controller (DMA) UM0306
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7 DMA controller (DMA)
7.1 Introduction
Direct Memory Access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The DMA controller has 7 channels, each dedicated to managing memory access requests
from one or more peripherals. It has an arbiter for handling the priority between DMA
requests.
7.2 Main features
● 7 independently configurable channels (requests)
● Each of the 7 channels is connected to dedicated hardware DMA requests, software
trigger is also supported on each channel. This configuration is done by software.
● The priorities between the seven requests is software programmable (4 levels
consisting of very high, high, medium, low) or hardware in case of equality (request 1
has priority over request 2, etc.)
● Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking.
● Support for circular buffer management
● 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
● Memory-to-memory transfer
● Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
● Access to Flash, SRAM, peripheral SRAM, APB1 and APB2 peripherals as source and
destination
● Programmable number of data to be transferred: up to 65536
The block diagram is shown in Figure 16.
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