General purpose timer (TIMx) UM0306
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The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
Figure 94. Control circuit in external clock mode 1
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 95 gives an overview of the external trigger input block.
Figure 95. External trigger input block
For example, to configure the up-counter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
COUNTER CLOCK = CK_CNT = CK_PSC
COUNTER REGISTER
35 3634
TI2
CNT_EN
TIF
Write TIF=0
ETR
0
1
TIMx_SMCR
ETP
divider
/1, /2, /4, /8
ETPS[1:0]
ETRP
filter
ETF[3:0]
down-counter
CK_INT
TIMx_SMCR
TIMx_SMCR
ETR pin
CK_INT
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
etrf
trgi
ti1f
ti2f
or
or
or
(internal clock)
ck_psc
ECE
TIMx_SMCR
SMS[2:0]
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