UM0306 DMA controller (DMA)
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Table 2 9 lists the DMA requests for each channel.
7.4 DMA registers
Refer to Section 1.1 on page 23 for a list of abbreviations used in the register descriptions.
7.4.1 DMA interrupt status register (DMA_ISR)
Address Offset: 00h
Reset Value: 0000 0000 (00h)
Table 29. Summary of DMA requests for each channel
Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7
ADC
ADC1
SPI
SPI1_RX SPI1_TX SPI2_RX SPI2_TX
USART
USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX
I
2
C
I2C2_TX I2C2_RX I2C1_TX I2C1_RX
TIM1
TIM1_CH1 TIM1_CH2
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM1_UP TIM1_CH3
TIM2
TIM2_CH3 TIM2_UP TIM2_CH1
TIM2_CH2
TIM2_CH4
TIM3
TIM3_CH3
TIM3_CH4
TIM3_UP
TIM3_CH1
TIM3_TRIG
TIM4
TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_UP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5
rrrrrrrrrrrr
1514131211109876543210
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
rrrrrrr r r rrrrrrr
Bits 31:28 Reserved, always read as 0.
Bits 27, 23, 19,
15, 11, 7, 3
TEIFx: Channel x Transfer Error flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the
corresponding bit in the DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
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