UM0306 Advanced control timer (TIM1)
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12.4 Functional description
12.4.1 Time base unit
The main block of the programmable advanced control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The Time Base Unit includes:
● Counter Register (TIM1_CNT)
● Prescaler Register (TIM1_PSC):
● Auto-Reload Register (TIM1_ARR)
● Repetition Counter Register (TIM1_RCR)
The auto-reload register is preloaded. Writing or reading the auto-reload register access the
preload register. The content of the preload register is transferred in the shadow register
permanently or at each update event UEV, depending on the auto-reload preload enable bit
(ARPE) in TIM1_CR1 register. The update event is sent when the counter reaches the
overflow (or underflow when down-counting) and if the UDIS bit equals 0 in the TIM1_CR1
register. It can also be generated by software. The generation of the update event is
described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIM1_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIM1_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 25 and Figure 26 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:
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