UM0306 General purpose timer (TIMx)
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Note: The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO and AFIO registers.
13.5.10 Counter (TIMx_CNT)
Address offset: 24h
Reset value: 0000h
13.5.11 Prescaler (TIMx_PSC)
Address offset: 28h
Reset value: 0000h
Table 40. Output control bit for standard OCx channels
CCxE bit OCx output state
0 Output Disabled (OCx=0, OCx_EN=0)
1 OCx=OCxREF + Polarity, OCx_EN=1
1514131211109876543210
CNT[15:0]
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Bits 15:0 CNT[15:0]: Counter Value.
1514131211109876543210
PSC[15:0]
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Bits 15:0
PSC[15:0]: Prescaler Value.
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update
event.
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