ST STM32F10 Series User Manual

Controller area network (bxCAN) UM0306
290/519
Figure 125. Receive FIFO states
FIFO management
Starting from the empty state, the first valid message received is stored in the FIFO which
becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CRFR
register to the value 01b. The message is available in the FIFO output mailbox. The software
reads out the mailbox content and releases it by setting the RFOM bit in the CRFR register.
The FIFO becomes empty again. If a new valid message has been received in the
meantime, the FIFO stays in pending_1 state and the new message is available in the
output mailbox.
If the application does not release the mailbox, the next valid message will be stored in the
FIFO which enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for
the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this
point, the software must release the output mailbox by setting the RFOM bit, so that a
mailbox is free to store the next valid message. Otherwise the next valid message received
will cause a loss of message.
Refer also to Section 14.5.5: Message storage
Overrun
Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid
message reception will lead to an overrun and a message will be lost. The hardware
EMPTY
Valid Message
FMP=0x00
FOVR=0
PENDING_1
FMP=0x01
FOVR=0
Received
PENDING_2
FMP=0x10
FOVR=0
PENDING_3
FMP=0x11
FOVR=0
Valid Message
Received
Release
OVERRUN
FMP=0x11
FOVR=1
Mailbox
Release
Mailbox
Valid Message
Received
Valid Message
Received
Release
Mailbox
Release
Mailbox
Valid Message
Received
RFOM=1
RFOM=1
RFOM=1
www.BDTIC.com/ST

ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English