Independent watchdog (IWDG) UM0306
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10.2.3 Reload register (IWDG_RLR)
Address Offset: 08h
Reset value: 00000FFFh (reset by STANDBY mode)
10.2.4 Status register (IWDG_SR)
Address Offset: 0Ch
Reset value: 00000000h (not reset by STANDBY mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved RL[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:12 Reserved, read as 0.
Bits11:0
RL[11:0]: Watchdog counter reload value
These bits are write access protected see Section 10.1.2. They are written by
software to define the value to be loaded in the watchdog counter each time
the value AAAAh is written in the IWDG_KR register. The watchdog counter
counts down from this value. The time-out period is a function of this value and
the clock prescaler. Refer to Table 33.
The RVU bit in the IWDG_SR register must be reset in order to be able to
change the reload value.
Note: reading this register returns the reload value from the VDD voltage
domain. This value may not be up to date/valid if a write operation to this register
is ongoing on this register. For this reason the value read from this register is
valid only when the RVU bit in the IWDG_SR register is reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved RVU PVU
rr
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