ST STM32F10 Series User Manual

Advanced control timer (TIM1) UM0306
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12.5.10 Counter (TIM1_CNT)
Address offset: 24h
Reset value: 0000h
12.5.11 Prescaler (TIM1_PSC)
Address offset: 28h
Reset value: 0000h
12.5.12 Auto-reload register (TIM1_ARR)
Address offset: 2Ch
Reset value: 0000h
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CNT[15:0]
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Bits 15:0 CNT[15:0]: Counter Value.
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PSC[15:0]
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Bits 15:0
PSC[15:0]: Prescaler Value.
The counter clock frequency (CK_CNT) is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update
event (including when the counter is cleared through UG bit of TIM1_EGR register or
through trigger controller when configured in “reset mode”).
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ARR[15:0]
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Bits 15:0
ARR[15:0]: Prescaler Value.
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 12.4.1: Time base unit on page 153 for more details about ARR
update and behavior.
The counter is blocked while the auto-reload value is null.
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ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English