UM0306 Advanced control timer (TIM1)
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12.5.2 Control register 2 (TIM1_CR2)
Address offset: 04h
Reset value: 0000h
1514131211109876543210
Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Res. CCPC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 Reserved, always read as 0
Bit 14
OIS4: Output Idle state 4 (OC4 output).
refer to OIS1 bit
Bit 13
OIS3N: Output Idle state 3 (OC3N output).
refer to OIS1N bit
Bit 12
OIS3: Output Idle state 3 (OC3 output).
refer to OIS1 bit
Bit 11
OIS2N: Output Idle state 2 (OC2N output).
refer to OIS1N bit
Bit 10
OIS2: Output Idle state 2 (OC2 output).
refer to OIS1 bit
Bit 9
OIS1N: Output Idle state 1 (OC1N output).
0: OC1N=0 after a dead-time when MOE=0
1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIM1_BKR register).
Bit 8
OIS1: Output Idle state 1 (OC1 output).
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIM1_BKR register).
Bit 7
TI1S: TI1 Selection.
0: The TIM1_CH1 pin is connected to TI1 input.
1: The TIM1_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR
combination)