ST STM32F10 Series User Manual

Advanced control timer (TIM1) UM0306
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Bits 6:4
MMS[1:0]: Master Mode Selection.
These bits allow to select the information to be sent in master mode to slave timers
for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIM1_EGR register is used as trigger output
(TRGO). If the reset is generated by the trigger input (slave mode controller
configured in reset mode) then the signal on TRGO is delayed compared to the
actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO).
It is useful to start several timers at the same time or to control a window in which a
slave timer is enable. The Counter Enable signal is generated by a logic OR between
CEN control bit and the trigger input when configured in gated mode. When the
Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in
TIM1_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a
master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag
is to be set (even if it was already high), as soon as a capture or a compare match
occurred. (TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
110: Compare - OC3REF signal is used as trigger output (TRGO).
111: Compare - OC4REF signal is used as trigger output (TRGO).
Bit 3
CCDS: Capture/Compare DMA Selection.
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bit 2
CCUS: Capture/Compare Control Update Selection.
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by
setting the COM bit only.
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by
setting the COM bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, always read as 0
Bit 0
CCPC: Capture/Compare Preloaded Control.
0: CCxE, CCxNE and OCxM bits are not preloaded
1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are
updated only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.
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ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English