ST STM32F10 Series User Manual

UM0306 Reset and clock control (RCC)
65/519
4.3.7 APB2 Peripheral Clock enable register (RCC_APB2ENR)
Address: 18h
Reset value: 0000 0000h
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in APB2 domain
is on going. In this case, wait states are inserted until this access to APB2 peripheral is
finished.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109 87654321 0
Res;
USAR
T1
EN
Res;
SPI1
EN
TIM1
EN
ADC2
EN
ADC1
EN
Reserved
IOPE
EN
IOPD
EN
IOPC
EN
IOPB
EN
IOPA
EN
Res.
AFIO
EN
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, always read as 0.
Bit 14
USART1EN USART1 clock enable
Set and reset by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, always read as 0.
Bit 12
SPI1EN SPI 1 clock enable
Set and reset by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled
Bit 11
TIM1EN TIM1 Timer clock enable
Set and reset by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
Bit 10
ADC2EN ADC 2 interface clock enable
Set and reset by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
Bit 9
ADC1EN ADC 1 interface clock enable
Set and reset by software.
0: ADC 1 interface disabled
1: ADC 1 interface clock enabled
Bits 8:7 Reserved, always read as 0.
www.BDTIC.com/ST

ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English