UM0306 General purpose and alternate function I/O (GPIO and AFIO)
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5.4 AFIO register description
Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.
Event control register (AFIO_EVCR)
Address Offset: 00h
Reset value: 0x0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved EVOE PORT[2:0] PIN[3:0]
rw rw rw rw rw rw rw rw
Bits 31:18
Bit 7
EVOE Event Output Enable
Set and cleared by software. When set the EVENTOUT Cortex output is
connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits.
Bits 6:4
PORT[2:0]: Port selection
Set and cleared by software. Select the port used to output the Cortex
EVENTOUT signal.
000: PA selected
001: PB selected
010: PC selected
011: PD selected
100: PE selected
Bits 3:0
PIN[3:0] Pin selection (x = A .. E)
Set and cleared by software. Select the pin used to output the Cortex
EVENTOUT signal.
0000: Px0 selected
0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected
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