UM0306 General purpose and alternate function I/O (GPIO and AFIO)
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5 General purpose and alternate function I/O (GPIO and
AFIO)
5.1 GPIO functional description
Each of the General Purpose I/O Ports has two 32-bit configuration registers (GPIOx_CRL,
GPIOx_CRH, two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset
register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register
(GPIOx_LCKR).
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
in several modes:
– Input floating
– Input Pull-up
– Input-Pull-down
– Analog Input
– Output Open-Drain
– Output Push-Pull
– Alternate Function Push-Pull
– Alternate Function Open-Drain
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed
as 32-bit words (half-word or byte accesses are not allowed). The purpose of the
GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of
the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the
modify access.
Figure 9 shows the basic structure of an I/O Port bit.
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