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UM0306 Inter-integrated circuit (I2C) interface

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Slave receiver

Following the address reception and after clearing ADDR, the slave receives bytes from the

SDA line into the DR register via the internal shift register. After each byte the interface

generates in sequence:

● An acknowledge pulse if the ACK bit is set

● The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and

ITBUFEN bit is set.

If RxNE is set and the data in the DR register is not read before the end of the last data

reception, the BTF bit is set and the interface waits for a read to the DR register, stretching

SCL low (see Figure 136 Transfer sequencing).

Figure 136. Transfer sequence diagram for slave receiver

Closing slave communication

After the last data byte is transferred a Stop Condition is generated by the master. The

interface detects this condition and sets,

● The STOPF bit and generates an interrupt if the ITEVFEN bit is set.

Then the interface waits for a read of the SR1 register followed by a write to the CR1 register

(see Figure 136 Transfer sequencing EV4).

7-bit Slave receiver:

10-bit Slave receiver:

Legend: S= Start, S

= Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,

EVx= Event (with interrupt if ITEVFEN=1)

EV1: ADDR=1, cleared by reading SR1 followed by reading SR2

EV2: RxNE=1 cleared by reading DR register.

EV4: STOPF=1, cleared by reading SR1 register followed by writing to the CR1 register

S Address A Data1 A Data2 A

.....

DataN A P

EV1 EV2 EV2 EV2 EV4

S Header A Address A Data1 A

.....

DataN A P

EV1 EV2 EV2 EV4

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