UM0306 Memory and bus architecture
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DMA bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.
BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of
three masters (CPU DCode, System bus and DMA bus) and three slaves (FLITF, SRAM,
and AHB2APB bridges).
AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.
AHB/APB bridges (APB)
The two AHB/APB bridges provide full synchronous connections between the AHB and the
2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz
depending on device).
Refer to Table 1 on page 27 for the address mapping of the peripherals connected to each
bridge.
2.2 Memory organization
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
Figure 2 on page 26 shows the STM32F10x Memory Map. For the detailed mapping of
peripheral registers, please refer to the related chapters.
The addressable memory space is divided into 8 main blocks, each of 512MB.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved” (gray shaded areas in the Figure 2 on page 26).
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