UM0306 Serial peripheral interface (SPI)
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SSM and SSI bits in the SPI_CR1 register.
If the NSS pin is required in output mode, just the SSOE bit should be set.
6. The MSTR and SPE bits must be set (they remain set only if the NSS pin is connected
to a high level signal).
In this configuration the MOSI pin is a data output and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is written in the Tx Buffer.
The data byte is parallel loaded into the shift register (from the internal bus) during first bit
transmission and then shifted out serially to the MOSI pin MSB first or LSB first depending
on the LSBFIRST bit in the SPI_CR1 register. The TXE flag will be set on the transfer of
data from the Tx Buffer to the shift register and an interrupt will be generated if TXEIE bit in
the SPI_CR2 register is set.
For the receiver, when data transfer is complete
● The Data in shift register is transferred to RX Buffer and the RXNE flag is set.
● An Interrupt is generated if the RXEIE bit is set in the SPI_CR2 register
At the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the
shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI
peripheral returns this buffered value.
Clearing the RXNE bit is performed by reading the SPI_DR register.
A continuous transmit stream can be maintained if the next data to be transmitted is put in
the Tx buffer once the transmission is started. Note that TXE flag should be ‘1’ before an
attempt to write the Tx buffer.
16.3.4 Simplex communication
The SPI is capable of operating in simplex mode in 2 configurations.
● 1 clock and 1 bidirectional data wire
● 1 clock and 1 data wire (Rx-only or full duplex)
1 Clock and 1 bidirectional data wire
This mode is enabled by setting the BIDIMODE bit in the SPI_CR2 register. In this mode
SCK is used for the clock and MOSI in master or MISO in slave mode is used for data
communication. The transfer direction (Input/Output) is selected by the BIDIOE bit in the
SPI_CR2 register. When this bit is 1, the data line is output otherwise it is input.
1 Clock and 1 data wire (Rx-only or full duplex)
In order to free an I/O pin so it can be used for other purposes, it is possible to disable the
SPI output function by setting the RXONLY bit in the SPI_CR1 register. In this case, SPI will
function in Receive-only mode. When the RXONLY bit is reset, the SPI will function in full
duplex mode.
Receive-only mode
To start the communication in receive-only mode, it is necessary to enable the SPI. In the
master mode, the communication starts immediately and will stop when the SPE bit is reset
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