Serial peripheral interface (SPI) UM0306
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and the current reception terminates. In slave mode, the SPI will continue to receive as long
as the NSS is pulled down (or the SSI bit is reset) and the SCK is running.
Note: The SPI can be used in Tx-only mode when the RXONLY bit in the SPI_CR1 register is
reset, the RX pin (MISO in master or MOSI in slave) can be used as GPIO. In this case,
when the data register is read, it does not contain the received value.
16.3.5 Status flags
There are three status flags to allow the application to completely monitor the state of the
SPI bus.
Busy flag
This flag indicates the state of the communication layer of the SPI. When it is set, it indicates
that the SPI is busy communicating and/or there is a valid data byte in the Tx buffer waiting
to be transmitted. The purpose of this flag is to indicate if there is any communication
ongoing on the SPI bus or not. This flag will be set as soon as:
1. Data is written in the SPI_DR register in master mode
2. The SCK clock is present in slave mode
The BUSY flag will reset as soon as a byte is transmitted/ received. This flag is set and reset
by hardware. This flag can be monitored to avoid write collision errors. Writing to this flag
has no effect. This flag has meaning only when the SPE bit is set.
Tx buffer empty flag (TXE)
This flag when set indicates that the Tx buffer is empty and the next data to be transmitted
can be loaded into the buffer. The TXE flag is reset when the Tx buffer already has a data
which is to be transmitted. This flag is reset when the SPI is disabled (SPE bit is reset).
Rx buffer not empty (RXNE)
This flag when set indicates that there is a valid received data in the Rx Buffer. This flag is
reset when SPI Data register is read.
16.3.6 CRC calculation
A CRC calculator has been implemented for communication reliability. Separate CRC
calculators are implemented for transmitted data and received data. The CRC is calculated
using a programmable polynomial serially on each bit. It is calculated on the sampling clock
edge defined by the CPHA and CPOL bits in the SPI_CR1 register.
Note: This SPI offers two kinds of CRC calculation standard which depend directly on the data
frame format selected for the transmission and/or reception: 8-bit data (CR8) and 16-bit data
(CRC16-CCITT).
CRC calculation is enabled by setting the CRCEN bit in the SPI_CR1 register. This action
resets the CRC registers (SPI_RXCRCR and SPI_TXCRCR).
In full-duplex mode, the CRC is automatically verified. However, in simplex mode, CRC
verification is performed through software by the receiver.
Note: Please refer to the product specs for availability of this feature.
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