UM0306 Serial peripheral interface (SPI)
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SPI communication using CRC is possible through the following procedure:
● Program the polynomial in the SPI_CRCPOLYR register
● Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This
also clears the SPI_RXCRCR and SPI_TXCRCR registers
● Program the CPOL, CPHA, LSBfirst, DFF, BR, SSM, SSI and MSTR values.
● Enable the SPI by setting the SPE bit in SPI_CR1
● Start the communication and sustain the communication until all but one byte or half-
word have been transmitted or received.
● In full-duplex mode:
– On writing the last byte of half-word to the Txbuffer, set the CRCNext bit in the
SPI_CR1 register to indicate that after transmission of the last byte, the CRC
should be transmitted. The CRC calculation will be frozen during the CRC
transmission.
– After transmitting the last byte or half word, the SPI transmits the CRC. CRCNext
bit is reset. The CRC is also received and compared against the SPI_RXCRCR
value. If the value does not match, the CRCERR flag in SPI_SR is set and an
interrupt can be generated when the ERRIE in the SPI_CR2 register is set.
● In simplex mode:
– At the end of the last byte or half word transmission, the transmitter needs to write
the SPI_TXCRC register into the SPI_DR register.
– As soon as the reception buffer of the receiver is loaded with the CRC value sent
by the transmitter, the software has to read the SPI_RXCRC content. If it is equal
to 00 (in 8-bit mode) or 0000 (in 16-bit mode) the transfer is successful. For all
other values, the data transfer has been corrupted.
Note: With high bit rate frequencies, the user must take care when transmitting CRC. As the
number of used CPU cycles has to be as low as possible in the CRC transfer phase, the
calling of software functions in the CRC transmission sequence is forbidden to avoid errors
in the last data and CRC reception. This applies to only full-duplex mode since, in simplex
mode, the transfer of CRC is done by software and not automatically via the CRCNEXT bit.
For high bit rate frequencies, the DMA mode is advised to avoid degradation of SPI speed
performance due to CPU accesses impacting the SPI bandwidth.
16.3.7 SPI communication using DMA
To operate at its maximum speed, the SPI needs to be fed with the data for transmission and
the data received on the Rx buffer should be read to avoid overrun. To facilitate the transfers,
SPI is implemented with a DMW facility with a simple request/acknowledge protocol. The
DMA access is requested when the enable bit in the SPI_CR2 register is enabled. There are
separate requests for the Tx buffer and the Rx buffer.
Note: For high bit rate frequencies, the DMA mode is advised to avoid degradation of SPI speed
performance due to CPU accesses impacting the SPI bandwidth.
DMA capability with CRC (full-duplex mode)
When the SPI communication is enabled with the CRC communication along with the DMA
mode, the transmission and reception of the CRC bytes at the end of communication is
done automatically in full-duplex mode.
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