Serial peripheral interface (SPI) UM0306
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At the end of data and CRC transfers, the flag CRCERR of SPI-SR is set if corruption occurs
during the transfer
DMA capability with CRC (simplex mode)
In simplex together with DMA, the CRC is transmitted automatically to the receiver at the
end of the last DMA data transmission.
As soon as the reception buffer of the receiver is loaded with the CRC value sent by the
transmitter, the software has to read the SPI_RXCRC content. If it is equal to 00 (in 8-bit
mode) or 0000 (in 16-bit mode) the transfer is successful. For all other values, the data
transfer has been corrupted.
16.3.8 Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device has its NSS pin pulled low (in hardware
mode) or SSI bit low (in software mode), this automatically sets the MODF bit. Master mode
fault affects the SPI peripheral in the following ways:
● The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.
● The SPE bit is reset. This blocks all output from the device and disables the SPI
interface.
● The MSTR bit is reset, thus forcing the device into slave mode.
Use the following software sequence to clear the MODF bit:
1. Make a read or write access to the SPI_SR register while the MODF bit is set.
2. Then write to the SPI_CR1 register.
To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin
must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can
be restored to their original state during or after this clearing sequence.
As a security, hardware does not allow the setting of the SPE and MSTR bits while the
MODF bit is set.
In a slave device the MODF bit cannot be set. However, in a multi-master configuration, the
device can be in slave mode with this MODF bit set. In this case, the MODF bit indicates that
there might have been a multi-master conflict for system control. An interrupt routine can be
used to recover cleanly from this state by performing a reset or returning to a default state.
Overrun condition
An overrun condition occurs when the master device has sent data bytes and the slave
device has not cleared the RXNE bit resulting from the previous data byte transmitted.
When an overrun condition occurs:
● OVR bit is set and an interrupt is generated if the ERRIE bit is set.
In this case, the receiver buffer contents will not be updated with the newly received data
from the master device. A read to the SPI_DR register returns this byte. All other
subsequently transmitted bytes are lost.
Clearing the OVR bit is done by a read of the SPI_DR register followed by a read access to
the SPI_SR register.
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