UM0306 Advanced control timer (TIM1)
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Bit 1
CC1G: Capture/Compare 1 Generation.
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIM1_CCR1 register. The CC1IF flag
is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF
flag is set if the CC1IF flag was already high.
Bit 0
UG: Update Generation.
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initialize the counter and generates an update of the registers. Note that the
prescaler counter is cleared too (anyway the prescaler ratio is not affected). The
counter is cleared if the center-aligned mode is selected or if DIR=0 (up-counting),
else it takes the auto-reload value (TIM1_ARR) if DIR=1 (down-counting).
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