UM0306 Advanced control timer (TIM1)
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Bit 1
CC1IF: Capture/Compare 1 interrupt Flag.
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with
some exception in center-aligned mode (refer to the CMS bits in the TIM1_CR1
register description). It is cleared by software.
0: No match.
1: The content of the counter TIM1_CNT has matched the content of the
TIM1_CCR1 register.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIM1_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIM1_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity).
Bit 0
UIF: Update interrupt Flag.
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are
updated:
– At overflow or underflow regarding the repetition down-counter value (update if
REP_CNT=0) and if the UDIS=0 in the TIM1_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIM1_EGR register, if
URS=0 and UDIS=0 in the TIM1_CR1 register.
– When CNT is reinitialized by a trigger event (refer to Section 12.5.3: Slave mode
control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIM1_CR1 register.
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