ST STM32F10 Series - Page 68

Reset and clock control (RCC) UM0306
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Bit 21
I2C1EN I2C 1 clock enable
Set and reset by software.
0: I2C 1 clock disabled
1: I2C 1 clock enabled
Bits 20:17 Reserved, always read as 0.
Bit 18
USART3EN USART 3 clock enable
Set and reset by software.
0: USART 3 clock disabled
1: USART 3 clock enabled
Bit 17
USART2EN USART 2 clock enable
Set and reset by software.
0: USART 2 clock disabled
1: USART 2 clock enabled
Bits 16:15 Reserved, always read as 0.
Bit 14
SPI2EN SPI 2 clock enable
Set and reset by software.
0: SPI 2 clock disabled
1: SPI 2 clock enabled
Bits 13:12 Reserved, always read as 0.
Bit 11
WWDGEN Window Watchdog clock enable
Set and reset by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:3 Reserved, always read as 0.
Bit 2
TIM4EN Timer 4 clock enable
Set and reset by software.
0: Timer 4 clock disabled
1: Timer 4 clock enabled
Bit 1
TIM3EN Timer 3 clock enable
Set and reset by software.
0: Timer 3 clock disabled
1: Timer 3 clock enabled
Bit 0
TIM2EN Timer 2 clock enable
Set and reset by software.
0: Timer 2 clock disabled
1: Timer 2 clock enabled
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