UM0306 General purpose timer (TIMx)
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13.5 TIMx register description
Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.
13.5.1 Control register 1 (TIMx_CR1)
Address offset: 00h
Reset value: 0000h
1514131211109876543210
Reserved CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN
rw rw rw rw rw rw rw rw rw rw
Bits 15:10 Reserved, always read as 0
Bits 9:8
CKD: Clock Division.
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency
and sampling clock used by the digital filters (ETR, TIx),
00: T
DTS
=T
ck_tim
01: T
DTS
=2*T
ck_tim
10: T
DTS
=4*T
ck_tim
11: Reserved
Bit 7
ARPE: Auto-Reload Preload enable.
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:5
CMS: Center-aligned Mode Selection.
00: Edge-aligned mode. The counter counts up or down depending on the direction
bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output
compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx
register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output
compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx
register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output
compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx
register) are set both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as
long as the counter is enabled (CEN=1)
Bit 4
DIR: Direction.
0: Counter used as up-counter.
1: Counter used as down-counter.
Note: This bit is read only when the timer is configured in Center-aligned mode or
Encoder mode.
Bit 3
OPM: One Pulse Mode.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN).
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