UM0306 General purpose timer (TIMx)
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13.5.2 Control register 2 (TIMx_CR2)
Address offset: 04h
Reset value: 0000h
1514131211109876543210
Reserved TI1S MMS[2:0] CCDS Reserved
rw rw rw rw rw
Bits 15:8 Reserved, always read as 0.
Bit 7
TI1S: TI1 Selection.
0: The TIMx_CH1 pin is connected to TI1 input.
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR
combination)
See also Section 12.4.18: Interfacing with Hall sensors on page 185
Bits 6:4
MMS: Master Mode Selection.
These bits allow to select the information to be sent in master mode to slave timers
for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output
(TRGO). If the reset is generated by the trigger input (slave mode controller
configured in reset mode) then the signal on TRGO is delayed compared to the
actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO).
It is useful to start several timers at the same time or to control a window in which a
slave timer is enabled. The Counter Enable signal is generated by a logic OR
between CEN control bit and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on
TRGO, except if the master/slave mode is selected (see the MSM bit description in
TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a
master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag
is to be set (even if it was already high), as soon as a capture or a compare match
occurred. (TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
110: Compare - OC3REF signal is used as trigger output (TRGO).
111: Compare - OC4REF signal is used as trigger output (TRGO).
Bit 3
CCDS: Capture/Compare DMA Selection.
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, always read as 0