ST STM32F10 Series User Manual

UM0306 General purpose timer (TIMx)
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13.5.5 Status register (TIMx_SR)
Address offset: 10h
Reset value: 0000h
1514131211109876543210
Reserved
CC4
OF
CC3
OF
CC2
OF
CC1
OF
Reserved TIF Res. CC4IF CC3IF CC2IF CC1IF UIF
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Bit 15:13 Reserved, always read as 0.
Bit 12
CC4OF: Capture/Compare 4 Overcapture Flag.
refer to CC1OF description
Bit 11
CC3OF: Capture/Compare 3 Overcapture Flag.
refer to CC1OF description
Bit 10
CC2OF: Capture/Compare 2 Overcapture Flag.
refer to CC1OF description
Bit 9
CC1OF: Capture/Compare 1 Overcapture Flag.
This flag is set by hardware only when the corresponding channel is configured in
input capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, always read as 0.
Bit 6
TIF: Trigger interrupt Flag.
This flag is set by hardware on trigger event (active edge detected on TRGI input
when the slave mode controller is enabled in all modes but gated mode, both edges
in case gated mode is selected). It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bit 5 Reserved, always read as 0.
Bit 4
CC4IF: Capture/Compare 4 interrupt Flag.
refer to CC1IF description
Bit 3
CC3IF: Capture/Compare 3 interrupt Flag.
refer to CC1IF description
Bit 2
CC2IF: Capture/Compare 2 interrupt Flag.
refer to CC1IF description
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ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English